1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology, and more particularly, to a semiconductor system for controlling command scheduling and an operating method thereof.
2. Description of the Related Art
In a semiconductor system having a multi-rank structure, a memory controller may perform a scheduling operation to generate a command corresponding to a request having a higher priority among read or write requests from a host. A semiconductor system performing such an operation will be described with reference to FIG. 1.
FIG. 1 is a configuration diagram illustrating a conventional semiconductor system.
Referring to FIG. 1, the semiconductor system may include a host 110, a command queue 120, an arbitration unit 140, a command generation unit 150, and a semiconductor memory device 160.
The command queue 120, the arbitration unit 140, and the command generation unit 150 may be incorporated in one memory controller.
The command queue 120 may include an address mapping unit 121. The command queue 120 may include a plurality of command queues 131 to 133. The address mapping unit 121 may receive a plurality of requests REQ from the host 110. The address mapping unit 121 may convert physical addresses corresponding to each of the received requests REQ into logical addresses. For example, the address mapping unit 121 may perform an exclusive disjunction operation XOR on the physical addresses and corresponding key data. The addresses outputted from the address mapping unit 121 may include commands and/or addresses CMD/ADD. The addresses may include rank, bank, column, and row addresses. The commands may be or include a read, write, and/or erase command.
The plurality of command queues 131 to 133 can sequentially store the requests containing the command and address information outputted from the address mapping unit 121 according to bank and rank information contained in the requests.
The arbitration unit 140 may perform a scheduling operation to preferentially output a request having a higher priority depending on scoring values of the plurality of requests stored in the command queue 120. A scoring value may be obtained by combining QOS (Quality of Service), seniority, and row hit information for the respective requests. The seniority information may indicate how long a request has been stored in the command queue 120. The row hit information may indicate whether a corresponding request has the same row address as a previous request or an immediately previous request.
The arbitration unit 140 may determine the priorities of a plurality of requests based on their respective scoring values. The arbitration unit 140 may then sequentially output the requests according to their respective determined priorities.
The command generation unit 150 may generate a plurality of commands corresponding to each of the requests which are sequentially outputted from the arbitration unit 140. The command generation unit 150 may output the plurality of commands via an interface to a semiconductor memory device. The semiconductor memory device 160 may receive a command generated by the command generation unit 150 via the interface. The semiconductor memory device 160 may perform a command operation based on the command received.
In short, the memory controller may schedule the plurality of requests received from the host 110 based on the scoring values of the requests, and generate a command according to the priorities of the requests. The semiconductor memory device 160 may perform an internal operation in response to the command.
For example, a DDR4 semiconductor memory device may receive six commands from an external device during 35 ns, but allow only four activations during 35 ns due to a tFAW (Four-bank activation window) restriction. Thus, although the memory controller may output the six commands, the semiconductor memory device 160 may be activated to perform an operation according to the former four commands. However, the semiconductor memory device 160 cannot perform an operation corresponding to the latter two commands. Thus, the semiconductor memory device 160 may generate a performance overhead of 33%.